Projects

    • Government Funded Research Projects
        • “EDA solutions for memory-centric AI edge: system evaluation and implementation for reconfigurability,” Nov 2019–Oct 2022, Ministry Of Science and Technology (MOST) 3-year ERI Project
        • “Machine and Deep Learning Based Circuit and Layout Synthesis for Digital and Analog Designs,” Aug 2019–Jul 2022, Ministry Of Science and Technology (MOST) 3-Year Project
        • “Routing in Cyberphysical Active-Matrix Based Digital Microfluidic Biochips,” Aug 2017–Jul 2019, Ministry Of Science and Technology (MOST) 2-Year Project
        • “Advanced Low Voltage High-Speed Low-Power Memory Design,” Aug 2017–Jul 2019, MOST IndustrialAcademic Technology Consortium Integrated Research Project
        • “Ambient Analytics in Intelligent Manufacturing–Main Project and Subproject 3: Analog Layout Prototyping via Deep Learning,” Aug 2016–Jul 2019, MOST Integrated Research Project
        • “Data Analytics Based Electronic Design Automation–Subproject 2: Datapath Identification and Placement via Customized Clustering and Learning,” May 2014–Apr 2016, MOST Integrated Research Project
        • “Electronic Design Automation for Large Scale Microfluidic Biochip –Subproject 2: The Study of Fluid Routing Automation and Design Integration for Microfluidic Biochip,” May 2014–Apr 2016, MOST Integrated Research Project
        • “Parallel and Distributed Electronic Design Automation–Main Project and Subproject 2: Parallel and Distributed Algorithms in Mixed-Size Placement Optimization,” May 2011–Jul 2014, National Science Council (NSC) Integrated Research Project
        • “Electronic Design Automation for 3D Integration–Main Project and Subproject 4: 3D-SIC and 3D-SIP Design Planning,” Aug 2009–Jul 2011, NSC Integration Project
        • “A Novel Methodology in Chip-Package-Board Co-design and Co-optimization,” Aug 2008–Jul 2011, NSC 3-Year Research Project
        • “On Increasing Design Reliability in Advanced Manufacturing Technology–Main Project and Subproject 3: Yield Improvement Methodologies in Post-Layout Design Flow and Design for Test,” Aug 2006–Jul 2009, NSC Integrated Research Project
        • “Core Technology for e-Home Environment–Subproject 6: Power Supply Planning and Noise Avoidance in SoC Floorplan Design,” Aug 2004–Jul 2007, NSC Integrated Research Project
        • “System-on-Chip IP Collections and Verification,” Apr 2004–Mar 2007, Ministry of Economic Affairs (MOEA) Integrated Research Project
        • “Design and Automation for Low-Power Systems–Subproject 7: Floorplanning with Aggressive Power Optimization,” Nov 2003–Jul 2006, NSC Integrated Research Project

 

    • Industry Funded Projects
        • “Advanced Node Cell Library Migration,” May 2021–Apr 2022, funded by NovaTek, Hsinchu, Taiwan
        • “Routability Improvement on DDIC APR,” Feb 2020–Jan 2021, funded by NovaTek, Hsinchu, Taiwan
        • “Timing Driven Partition for Multi-FPGA Architecture,” Dec 2019–Nov 2021, funded by Synopsys
        • “Power Integrity Optimization for Advanced 3DIC,” May 2019–Apr 2023, funded by TSMC, Taiwan
        • “Irregular Bump Style Package Design,” Jan 2018–Dec 2018, funded by MediaTek (MTK), Hsinchu, Taiwan
        • “Low Voltage High-Speed SRAM System Design,” Mar 2017–Jul 2019, funded by Etron, Taiwan
        • “System and Chip Level Power Network Optimization,” Jan 2017–present, funded by EOSL, Industrial Technology Research Institute of Taiwan (ITRI)
        • “Advanced Node Custom Layout Synthesis,” Jun 2015–May 2016, funded by TSMC, Taiwan
        • “Thermal and Stress Migration Study for Microbump Interconnect in BGA Package,” Sep 2012–Aug 2014, funded by SPIL, Taiwan
        • “3D IC Power Network Modeling and Synthesis,” Jan 2011–present, funded by ICRL, Industrial Technology Research Institute of Taiwan (ITRI)
        • “LDO Design and Automation,” Feb 2008–Jan 2009, funded by MediaTek (MTK), Hsinchu, Taiwan