Publications

 

    • Book Chapter
        1. H.-M. Chen, D.F. Wong, H. Zhou, F.Y. Young, H.H. Yang, and N. Sherwani, “Integrated Floorplanning and Interconnect Planning,” in Layout Optimization in VLSI Designs, Kluwer Academic Publishers, 2001
        2. K.-C. Wang and H.-M. Chen, “Multilevel Large-Scale Modules Floorplanning/Placement with Improved Neighborhood Exchange in Simulated Annealing,” in Simulated Annealing, Theory with Applications, Sciyo, 2010

 

    • ACM/IEEE Journal Papers [SCI, EI]
        1. H.-M. Chen, L.-D. Huang, I-M. Liu, and D.F. Wong, “Simultaneous Power Supply Planning and Noise Avoidance in Floorplan Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.24, no.4, pp.578-587, April 2005 (TCAD-Apr-05)
        2. H.-M. Chen, I-M. Liu, and D.F. Wong, “I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.25, no.11, pp.2552-2556, November 2006 (TCAD-Nov-06)
        3. Chia-Yi Chang and H.-M. Chen, “Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization,” IEEE Transactions on Very Large Scale Integration Systems, v.16, no.1, pp.108-112, January 2008 (TVLSI-Jan-08)
        4. C.-H. Lu, H.-M. Chen, and C.-N. Liu, “Effective Decap Insertion in Area-Array SoC Floorplan Design,” ACM Transactions on Design Automation of Electronic Systems, v.13, no.4, article 66, September 2008 (TODAES-Sep-08)
        5. R.-J. Lee and H.-M. Chen, “Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign,” IEEE Transactions on Very Large Scale Integration Systems, v.17, no.8, pp.1087-1098, August 2009 (TVLSI-Aug-09)
        6. M.-C. Wu, M.-C. Lu, H.-M. Chen, and J.-Y. Jou, “Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning,” ACM Transactions on Design Automation of Electronic Systems, 15(1), article 3, December 2009 (TODAES-Dec-09)
        7. C.-Y. Lin, H.-C. Lin, and H.-M. Chen, “On Reducing Test Power and Test Volume by Effective Pattern Compression Schemes,” IEEE Transactions on Very Large Scale Integration Systems, 18(8), pp.1220-1224, August 2010 (TVLSI-Aug-10)
        8. R.-J. Lee and H.-M. Chen, “Efficient Package Pin-Out Planning with System Interconnects Optimization for Package-Board Codesign,” IEEE Transactions on Very Large Scale Integration Systems, 19(5), May 2011 (TVLSI-May-11)
        9. R.-J. Lee and H.-M. Chen, “A Study of Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow,” ACM Transactions on Design Automation of Electronic Systems, 18(2), article 30, March 2013 (TODAES-Mar-13)
        10. C.-Y. Chin, C.-Y. Kuan, T.-Y. Tsai, H.-M. Chen and Y. Kajitani, “Escaped Boundary Pins Routing for High Speed Boards,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(3), March 2013 (TCAD-Mar-13)
        11. S.-Y. Liu, W.-T. Lo, C.-J. Lee, and H.-M. Chen, “Agglomerative- Based Flip-Flop Merging and Relocation for Signal Wirelength and Clock Tree Optimization,” ACM Transactions on Design Automation of Electronic Systems, 18(3) Article 40, July 2013 (TODAES-Jul-13)
        12. R.-J. Lee, H.-W. Hsu and H.-M. Chen, “Board- and Chip-Aware Package Wire Planning,” IEEE Transactions on Very Large Scale Integration Systems, 21(8), August 2013 (TVLSI-Aug-13)
        13. S.-Y. Liu, R.-G. Luo, S. Aroonsantidecha, C.-Y. Chin, and H.-M. Chen, “A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green Function,” IEEE Transactions on Very Large Scale Integration Systems, 22(6), June 2014 (TVLSI-Jun-14)
        14. S.-Y. Liu, C.-H. Chang, H.-M. Chen and T.-Y. Ho, “ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(9), September 2014 (TCAD-Sep-14)
        15. C.-K. Wang, Y.-C. Chang, H.-M. Chen, C.-Y. Chin, “Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation,” ACM Transactions on Design Automation of Electronics Systems, 20(1) Article 3, November 2014 (TODAES-Nov-14)
        16. P.-C. Pan, C.-Y. Chin, H.-M. Chen, T.-C. Chen, C.-C. Lee, and J.-C. Lin, “A Fast Prototyping Framework for Analog Layout Migration with Planar Preservation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(9), September 2015 (TCAD-Sep-15)
        17. G.-R. Lu, C.-H. Kuo, K.-C. Chiang, A. Banerjee and B. B. Bhattacharya, T.-Y. Ho, and H.-M. Chen, “Flexible Droplet Routing in Active-Matrix Based Digital Microfluidic Biochips,” ACM Transactions on Design Automation of Electronic Systems, 23(3), April 2018 (TODAES-Apr-18)
        18. G.-R. Lu, A. Banerjee, B. B. Bhattacharya, T.-Y. Ho, and H.-M. Chen, “Reliability Hardening Mechanisms in Cyber-Physical Digital-Microfluidic Biochips,” ACM Journal on Emerging Technologies in Computing, 14(3), October 2018 (JETC-Oct-18)
        19. H.-Y. Chi, C.-N. Liu, and H.-M. Chen, “Wire Load Oriented Analog Routing with Matching Constraints,” ACM Transactions on Design Automation of Electronics Systems (TODAES), 25(6), October 2020, Article 55
        20. A. Patyal, P.-C. Pan, Asha K A, H.-M. Chen and W.-Z. Chen, “Exploring Multiple Analog Placements with Partial-Monotonic Current Paths and Symmetry Constraints using PCP-SP,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 39(12), December 2020
        21. Asha K. A., L.-E. Hsu, A. Patyal, and H.-M. Chen, “Improving the Quality of RO-PUF by Principal Component Analysis (PCA),” ACM Journal on Emerging Technologies in Computing(JETC), 17(3), June 2021, Article 34
        22. H.-Y. Chi, Z.-J. Lin, C.-H. Hung, C.-N. Liu, and H.-M. Chen, “A Style-based Analog Layout Migration Technique with Complete Routing Behavior Preservation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Early Access

 

 

    • Other Journal Papers
        1. C.-H. Lu, H.-M. Chen, and C.-N. Liu, “An Effective Decap Insertion Method Considering Power Supply Noise During Floorplanning,” January 2008, Journal of Information Science and Engineering (JISE-Jan-08)
        2. Bruce Tseng and H.-M. Chen, “Dual-Vdd Voltage Island-Aware Buffered Routing Tree Construction,” International Journal of Electrical Engineering, April 2008 (IJEE-Apr-08)
        3. Y.-C. Lin, H.-A. Chien, C.-C. Shih, and H.-M. Chen, “A Multi-layer Obstacles-Avoiding Router Using X-Architecture,” WSEAS Transaction on Circuits and Systems, Issue 8, Volume 7, August 2008
        4. C.-Y. Lin, H.-C. Lin, and H.-M. Chen, “A Methodology with Selective Pattern Compression Schemes on Reducing Test Power and Test Volume,” International Journal of Electrical Engineering, 17(1), pp. 75-88, January 2010 (IJEE-Jan-10)
        5. C.-Y. Lin, L.-C. Hsu, and H.-M. Chen, “On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques,” IEICE Transactions on Electronics, vol. E93-C no. 3, pp.369-378, March 2010 (IEICE-Mar-10)
        6. C.-H. Lu, H.-M. Chen, and C.-N. Liu, “Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits,” Journal of Information Science and Engineering, January 2011 (JISE-Jan-11)
        7. C.-Y. Lin and H.-M. Chen, “A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost,” Journal of Information Science and Engineering, November 2011 (JISE-Nov-11)
        8. C.-H. Lu, H.-M. Chen, C.-N. Liu, W.-Y. Shih, “Package Routability and IR-Drop-Aware Finger/Pad Planning for Single Chip and Stacking IC Designs,” Integration, the VLSI Journal, May 2012 (Integration-May-12)
        9. J.-D. Li, C.-H. Kuo, G.-R. Lu, S.-J. Wang, Katherine S.-M. Li, T.-Y. Ho, H.-M. Chen and S. Hu, “Co-placement Optimization in Sensor-reusable Cyber-physical Digital Microfluidic Biochips, ” Microelectronics Journal 83, pp. 185-196, January, 2019

 

    • ACM/IEEE Conference/Workshop Papers
        1. H.-M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, and N. Sherwani, “Integrated Floorplanning and Interconnect Planning,” Proc. of IEEE/ACM International Conference on Computer-Aided Design, pp. 356-359, November 1999 (ICCAD-99)
        2. I-M. Liu, H.-M. Chen, T.-L. Chou, A. Aziz, and D.F. Wong, “Integrated Power Supply Planning and Floorplanning,” Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 589-594, January 2001 (ASP-DAC-01)
        3. M. Chen, D.F. Wong, W.-K. Mak, and H.H. Yang, “Faster and More Accurate Wiring Evaluation for Interconnect-Centric Floorplanning,” ACM Great Lakes Symposium on VLSI, pp. 62-67, March 2001 (GLSVLSI-01)
        4. H.-M. Chen, L.-D. Huang, I-M. Liu, M. Lai, and D.F. Wong, “Floorplanning with Power Supply Noise Avoidance,” Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 427-430, January 2003 (ASP-DAC-03)
        5. L.-D. Huang, H.-M. Chen, and D.F. Wong, “Global Wire Bus Configuration with Minimum Delay Uncertainty,” Proc. of IEEE/ACM Design, Automation and Test in Europe, pp. 50-55, March 2003 (DATE-03)
        6. H.-M. Chen, I-Min Liu, D.F. Wong, M. Shao, and L.-D. Huang, “I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design,” Proc. IEEE International Conference on Computer Design, pp. 562-567, October 2004 (ICCD-04)
        7. M. Shao, Y. Gao, L.-P. Yuan, H.-M. Chen, and Martin D.F. Wong, “Current Calculation on VLSI Signal Interconnects, ” Proc. of IEEE International Symposium on Quality of Electronic Design, pp. 580-585, March 2005 (ISQED-05)
        8. L.-C. Hsu and H.-M. Chen, “On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design,” Proc. of IEEE International Symposium on Quality of Electronic Design, pp. 451-456, March 2006 (ISQED-06)
        9. C.-Y. Chang and H.-M. Chen, “Design Migration from Peripheral ASIC Design to Area-IO FlipChip Design by Chip I/O Planning and Legalization,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, pp. 147-150, April 2006 (VLSI-DAT-06)
        10. K.-C. Wang and H.-M. Chen, “Multilevel Large-Scale Modules Placement with Refined Neighborhood Exchange,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, pp. 235-238, April 2006 (VLSI-DAT-06)
        11. H.-L. Chen and H.-M. Chen, “On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study,” Proc. of IEEE International System on Chip Conference, pp. 203-206, September 2006 (SOCC-06)
        12. M.-C. Lu, M.-C. Wu, H.-M. Chen, and H.-R. Jiang, “Performance Constraints Aware Voltage Island Generation in SoC Floorplan Design,” Proc. of IEEE International System on Chip Conference, pp. 211-214, September 2006 (SOCC-06)
        13. R.-J. Lee, M.-F. Lai, and H.-M. Chen, “Fast Flip-Chip Pin-Out Designation by Pin-Block Design and Floorplanning for Package-Board Codesign,” Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 804-809, January 2007 (ASP-DAC-07)
        14. C.-H. Lu, H.-M. Chen, and C.-N. Liu, “On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design,” Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 792-797, January 2007 (ASP-DAC-07)
        15. C.-Y. Chen, J.-D. Huang, and H.-M. Chen, “Microarchitecture-Aware Floorplanning for Processor Performance Optimization,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, pp. 116-119, April 2007 (VLSI-DAT-07)
        16. C.-Y. Yeh, H.-M. Chen, L.-D. Huang, W.-T. Wei, C.-H. Lu, and C.-N. Liu, “Using Power Gating Techniques in Area-Array SoC Floorplan Design,” Proc. of IEEE International System on Chip Conference, pp. 233-236, September 2007 (SOCC-07)
        17. C.-Y. Lin and H.-M. Chen, “A Selective Pattern-Compression Scheme for Power and Test-Data Reduction,” IEEE/ACM International Conference on Computer-Aided Design, pp. 520-525, November 2007 (ICCAD-07)
        18. M.-F. Lai and H.-M. Chen, “An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign,” Proc. of IEEE International Symposium on Quality of Electronic Design, pp. 604-607, March 2008 (ISQED-08)
        19. B. Tseng and H.-M. Chen, “Blockage and Voltage Island-Aware Dual-Vdd Buffered Tree Construction,” Proc. of ACM International Symposium on Physical Design, pp. 23-30, April 2008 (ISPD-08)
        20. C.-H. Shui and H.-M. Chen, “On Minimizing Topography Variation in Multi-Layer Oxide CMP Manufacturability,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, pp. 39-42, April 2008 (Best Paper Nominee)
        21. L.-C. Wei, H.-M. Chen, L.-D. Huang, and S. Xu, “Efficient and Optimal Post-Layout Double-Cut Via Insertion by Network Relaxation and Min-Cost Maximum Flow,” Proc. of ACM Great Lakes Symposium on VLSI, pp. 359-362, May 2008 (GLSVLSI-08)
        22. H.-H. Pan, H.-M. Chen, and C.-Y. Chang, “Buffer/Flip-Flop Block Planning for Power-IntegrityDriven Floorplanning,” Proc. of IEEE International Symposium on Quality of Electronic Design, pp. 488-493, March 2009 (ISQED-09)
        23. C.-H. Lu, H.-M. Chen, C.-N. Liu, and W.-Y. Shih, “Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design,” Proc. of IEEE/ACM Design, Automation and Test in Europe, pp. 845-850, April 2009 (DATE-09)
        24. Y.-L. Co, H.-M. Chen, and Y.-K. Cheng, “Coupling- and ECP-Aware Metal Fill for Improving Layout Uniformity in Copper CMP,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, pp. 122-125, April 2009 (Best Paper Award Nominee)
        25. B.-C. Chen, H.-M. Chen, L.-D. Huang, and P.-C. Pan, “A Stochastic-Based Efficient Critical Area Extractor on OpenAccess Platform,” Proc. of ACM Great Lakes Symposium on VLSI, May 2009 (GLSVLSI-09)
        26. C.-H. Lin and H.-M. Chen, “On Minimizing Various Sources of Noise and Meeting Symmetry Constraint in Mixed-Signal SoC Floorplan Design,” Asia Symposium on Quality of Electronic Design, July 2009 (ASQED-09)
        27. F.-Y. Fan, H.-M. Chen, and I-M. Liu, “On Preserving Signal Integrity in Technology Mapping,” ACM/IEEE International Workshop on Logic and Synthesis, July 2009 (IWLS-09)
        28. C.-C. Hsiao and H.-M. Chen, “On Distinguishing Process Corners for Yield Enhancement in Memory Compiler Generated SRAM,” Proc. of IEEE International Workshop on Memory Technology, Design, and Test, August 2009 (MTDT-09)
        29. R.-J. Lee and H.-M. Chen, “Efficient Package Pin-Out Planning with Chip-Package Interconnects Optimization,” Proc. of IEEE Electrical Design of Advanced Package and Systems Symposium, December 2009 (EDAPS-09)
        30. R.-J. Lee and H.-M. Chen, “Novel I/O-Bump Design and Optimization for Chip-Package Codesign,” Proc. of IEEE Electrical Design of Advanced Package and Systems Symposium, December 2009 (EDAPS-09)
        31. F.-Y. Fan, H.-M. Chen, and I-M. Liu, ”Technology Mapping with Crosstalk Noise Avoidance,” Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference, January 2010 (ASPDAC-10)
        32. C.-Y. Lin and H.-M. Chen, “A Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reduction,” Proc. of IEEE International Symposium on Quality of Electronic Design, March 2010 (ISQED-10)
        33. H.-Y. Li, Iris H.-R. Jiang, and H.-M. Chen, “Simultaneous Voltage Island Generation and Floorplanning,” Proc. of IEEE International System on Chip Conference, September 2010 (SOCC-10)
        34. Y.-A. Shih, T.-H. Tsai, and H.-M. Chen, “Path-Based Cell Flipping Optimization for Wirelength Reduction and Routability,” Proc. of IEEE TENCON, November 2010 (TENCON-10)
        35. C.-Y. Lin, Y.-W. Chen, W.-J. Chen, and H.-M. Chen, “Fast Detection and Analysis Schemes for System-in-Package in the Presence of RAM,” IEEE Workshop on RTL and High Level Testing, December 2010 (WRTLT-10)
        36. K.-S. Lin, H.-W. Hsu, R.-J. Lee, and H.-M. Chen, “Area-I/O RDL Routing for Chip-Package Codesign Considering Regional Assignment,” Proc. of IEEE Electrical Design of Advanced Package and Systems Symposium, December 2010 (EDAPS-10)
        37. R.-J. Lee and H.-M. Chen, “Row-Based Area-Array I/O Design Planning in Concurrent ChipPackage Design Flow,” Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference, January 2011 (ASP-DAC-11)
        38. C.-C. Tsai, T.-H. Lin, S.-H. Tsai, and H.-M. Chen, “Clock Planning for Multi-Voltage and MultiMode Designs,” Proc. of IEEE International Symposium on Quality of Electronic Design, March 2011 (ISQED-11)
        39. K.-H. Meng, P.-C. Pan, and H.-M. Chen, “Integrated Hierarchical Synthesis of Analog/RF Circuits with Accurate Performance Mapping,” Proc. of IEEE International Symposium on Quality of Electronic Design, March 2011 (ISQED-11)
        40. M.-C. Wu, H.-M. Chen, and J.-Y. Jou, “Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures,” Proc. of IEEE International Symposium on Quality of Electronic Design, March 2011 (ISQED-11)
        41. Y.-R. Chen, H.-M. Chen, and S.-Y. Liu, “Z-Cut First Timing Driven Placement for TSV-Based 3D ICs,” IEEE/ACM DATE 3D Integration Workshop, March 2011
        42. T.-Y. Tsai, R.-J. Lee, C.-Y. Chin, C.-Y. Kuan, H.-M. Chen, and Y. Kajitani, “On Routing Fixed Escaped Boundary Pins for High Speed Boards,” Proc. of IEEE/ACM Design, Automation and Test in Europe, March 2011 (DATE-11)
        43. C.-Y. Lin, H.-M. Chen, and W.-C. Fang, “A Low Noise and Robust 3D System-in-Package Test Scheme for Optical Biosensor,” IEEE/NIH Life Science Systems and Applications Workshop, April 2011 (LiSSA-11)
        44. Y.-R. Chen, H.-M. Chen, and S.-Y. Liu, “TSV-Based 3D-IC Placement for Timing Optimization,” Proc. of IEEE International System on Chip Conference, September 2011 (SOCC-11)
        45. Y.-P. Weng, H.-M. Chen, T.-C. Chen, P.-C. Pan, C.-H. Chen, and W.-Z. Chen, “Fast Analog Layout Prototyping for Nanometer Design Migration,” IEEE/ACM International Conference on Computer-Aided Design, November 2011 (ICCAD-11)
        46. Y.-C. Chang, C.-K. Wang and H.-M. Chen, “Slew Rate Aware Lower Power and More Robust Clock Tree Construction,” ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, January 2012 (TAU-12)
        47. S. Aroonsantidecha, S.-Y. Liu, C.-Y. Chin, and H.-M. Chen, “A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green Function,” Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference, January 2012 (ASP-DAC-12)
        48. Y.-C. Chang, C.-K. Wang and H.-M. Chen, “On Constructing Low Power and Robust Clock Tree via Slew Budgeting,” Proc. of ACM International Symposium on Physical Design, March 2012 (ISPD-12)
        49. C.-J. Lee, S.-Y. Liu, C.-C. Huang, H.-M. Chen, C.-T. Lin, and C.-H. Lee, “Hierarchical Power Network Synthesis for Multiple Power Domain Designs,” Proc. of IEEE International Symposium on Quality of Electronic Design, March 2012 (ISQED-12)
        50. H.-W. Hsu, M.-L. Chen, H.-M. Chen, and H. Chen, “On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer,” Proc. of IEEE/ACM Design, Automation and Test in Europe, March 2012 (DATE-12)
        51. S.-Y. Liu, C.-J. Lee, and H.-M. Chen, “Agglomerative Based Flip-Flop Merging for Power Optimization,” Proc. of IEEE/ACM Design, Automation and Test in Europe, March 2012 (DATE-12)
        52. P.-C. Pan, H.-M. Chen, Y.-K. Cheng, J. Liu and W.-Y. Hu, “Configurable Analog Routing Methodology via Technology and Design Constraint Unification,” Proc. of IEEE/ACM International Conference on Computer-Aided Design, November 2012 (ICCAD-12)
        53. S.-Y. Liu, R.-G. Luo, and H.-M. Chen, “A Network-Flow Based Algorithm For Power Density Mitigation at Post-Placement Stage,” Proc. of IEEE/ACM Design, Automation and Test in Europe, March 2013 (DATE-13)
        54. S.-Y. Liu, C.-J. Lee, C.-C. Huang, H.-M. Chen, C.-T. Lin, C.-H. Lee, “Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming,” Proc. of IEEE/ACM Design, Automation and Test in Europe, March 2013 (DATE-13)
        55. P.-C. Pan, H.-M. Chen and C.-C. Lin, “PAGE: Parallel Agile Genetic Exploration toward Utmost Performance for Analog Circuit Design,” Proc. of IEEE/ACM Design, Automation and Test in Europe, March 2013 (DATE-13)
        56. H.-M. Chen, “On the Way to Practical Tools for Beyond Die Codesign and Integration,” Proc. of ACM International Symposium on Physical Design, March 2013 (ISPD-13) (Invited)
        57. C.-C. Chen, W.-C. Wu, C.-Y. Chin, H.-M. Chen, V. Lin, E. Chen, “Mean-time-to-crack Model of Microbump Interconnect in FCBGA Package under Thermal Cyclic Test,” Proc. of IEEE International Workshop on Thermal Investigations of ICs and Systems (THERMINIC-13), September 2013
        58. C.-Y. Chin, P.-C. Pan, H.-M. Chen, T.-C. Chen and J.-C. Lin, “Efficient Analog Layout Prototyping by Layout Reuse with Routing Preservation,” Proc. of IEEE/ACM International Conference on Computer-Aided Design, November 2013 (ICCAD-13)
        59. Y.-J. Lee, H.-M. Chen, and C.-Y. Chin, “On Simultaneous Escape Routing of Length Matching Differential Signalings,” Proc. of IEEE Electrical Design of Advanced Package and Systems Symposium, December 2013 (EDAPS-13)
        60. C.-Y. Chin and H.-M. Chen, “Simultaneous Escape Routing on Multiple Components for Dense PCBs,” Proc. of IEEE Electrical Design of Advanced Package and Systems Symposium, December 2013 (EDAPS-13)
        61. M.-L. Chen, T.-H. Tsai, H.-M. Chen and S.-H. Chen, “Routability-Driven Bump Assignment for Chip-Package Co-Design,” Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference, January 2014 (ASP-DAC-14)
        62. Y.-E. Chen, T.-H. Tsai, S.-H. Chen and H.-M. Chen,“Cost-Effective Decap Selection for Beyond Die Power Integrity,” Proc. of IEEE/ACM Design, Automation and Test in Europe, March 2014 (DATE-14)
        63. Y. Shi and H.-M. Chen, “Memcomputing: the Cape of Good Hope,” Proc. of IEEE/ACM Design, Automation and Test in Europe, March 2014 (DATE-14)
        64. S.-H. Hsu, W.-Z. Chen, J.-P. Zheng, S.-Y. Liu, P.-C. Pan and H.-M. Chen, “An Automatic Synthesis Tool for Nanometer Low Dropout Regulator Using Simulation Based Model and Geometric Programming,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, April 2014 (VLSI-DAT-14)
        65. C-C. Huang, C.-T. Lin, W.-S. Liao, C.-J. Lee, H.-M. Chen, C.-H. Lee and D.-M. Kwai, “Improving Power Delivery Network Design by Practical Methodologies,” Proc. of IEEE International Conference on Computer Design, October 2014 (ICCD-14)
        66. H.-C. Lin, S.-Y. Liu and H.-M. Chen, “Planning and Placing Power Clamps for Effective CDM Protection,” Proc. of IEEE/ACM International Conference on Computer-Aided Design, November 2014 (ICCAD-14)
        67. S.-Y. Liu, T-C. Chen, and H.-M. Chen, “An Approach to Anchoring and Placing High Performance Custom Digital Designs,” Proc. of ACM/IEEE Asia and South Pacific Design Automation conference, January 2015 (ASP-DAC-15)
        68. C.-K Wang, C.-C. Huang, S.-Y. Liu, C.-Y. Chin, S.-T. Hu, W.-C. Wu and H.-M Chen, “Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability,” Proc. of ACM International Symposium on Physical Design, March 2015 (ISPD-15)
        69. Y.-H. Hung, S.-H. Fang, H.-M. Chen, S.-M. Chen, C.-T. Lin, and C.-H. Lee, “A New Methodology for Noise Sensor Placement Based on Association Rule Mining,” Proc. of ACM Great Lakes Symposium on VLSI, May 2016 (GLSVLSI-16) (Best Paper Award Nominee)
        70. C.-H. Kuo, G.-R. Lu, H.-M. Chen, T.-Y. Ho, and S. Hu, “Placement Optimization of CyberPhysical Digital Microfluidic Biochips,” Proc. of IEEE Biomedical Circuits and Systems Conference, October 2016 (BioCAS-16)
        71. G.-R. Lu, G.-M. Huang, A. Banerjee, B. B. Bhattacharya, T.-Y. Ho, and H.-M. Chen, “On Reliability Hardening in Cyber-Physical Digital-Microfluidic Biochips,” Proc. of ACM/IEEE Asia and South Pacific Design Automation conference, January 2017 (ASP-DAC-17)
        72. W.-H. Liao, C.-T. Lin, S.-H. Fang, C.-C. Huang, H.-M. Chen, D.-M. Kwai, and Y.-F. Chou, “Heterogeneous Chip Power Delivery Modeling and Co-Synthesis for Practical 3DIC Realization,” Proc. of ACM/IEEE Asia and South Pacific Design Automation conference, January 2017 (ASPDAC-17) (Invited)
        73. W.-N. Wu, C. Chen, C.-Y. Chin, C.-K. Wang, and H.-M. Chen, “An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, April 2017 (VLSI-DAT-17)
        74. S.-H. Fang, C.-T. Lin, W.-H. Liao, C.-C. Huang, L.-C. Chen, H.-M. Chen, I-H. Lee, D.-M. Kwai, and Y.-F. Chou, “On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC,” Proc. of IEEE Computer Society Annual Symposium on VLSI, July 2017 (ISVLSI-17)
        75. G.-R. Lu, B. B. Bhattacharya, T.-Y. Ho, and H.-M. Chen, “Multi-Level Droplet Routing in Active-Matrix Based Digital-Microfluidic Biochips,” Proc. of ACM/IEEE Asia and South Pacific Design Automation conference, January 2018 (ASP-DAC-18)
        76. H.-Y. Chi, H.-Y. Tseng, C.-N. Jimmy Liu, and H.-M. Chen, “Performance-Preserved Analog Routing Methodology via Wire Load Reduction,” Proc. of ACM/IEEE Asia and South Pacific Design Automation conference, January 2018 (ASP-DAC-18)
        77. L.-C. Chen, C.-C. Huang, Y.-L. Chang and H.-M. Chen, “A Learning-Based Methodology for Routability Prediction in Placement,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, April 2018 (VLSI-DAT-18)
        78. A. Patyal, P.-C. Pan, Asha K A, H.-M. Chen, H.-Y. Chi, and C.-N. Liu, “Analog Placement with Current Flow and Symmetry Constraints using PCP-SP,” Proc. of ACM/IEEE Design Automation Conference, June 2018 (DAC-18)
        79. P.-C. Pan, H.-W. Huang, C.-C. Huang, A. Patyal, H.-M. Chen and T.-Y. Yang, “On Closing the Gap Between Pre-simulation and Post-simulation Results in Nanometer Analog Layouts,” Proc. of International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, July 2018 (SMACD-18)
        80. B.-H. Jiang and H.-M. Chen, “Extending ML-OARSMT to Net Open Locator with Efficient and Effective Boolean Operations,” Proc. of IEEE/ACM International Conference on ComputerAided Design, November 2018 (ICCAD-18)
        81. Asha K A, A. Patyal, and H.-M. Chen, “Generation of PUF-Keys on FPGAs by K-means Frequency Clustering,” Proc. of IEEE Asian Hardware Oriented Security and Trust Symposium, December 2018 (AsianHOST-18)
        82. Y.-H. Chuang, C.-T. Lin, H.-M. Chen, C.-H. Lee and T.-S. Chen, “More Effective Power Network Prototyping by Analytical and Centroid Learning,” Proc. of IEEE International Symposium on Circuits and Systems, May 2019 (ISCAS-19)
        83. P.-C. Pan, C.-C Huang and H.-M. Chen, “An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis (LBR),” Proc. of ACM/IEEE Design Automation Conference, June 2019 (DAC-19)
        84. Y.-H. Chen, H.-Y. Chi, L.-Y. Song, C.-N. Liu and H.-M. Chen, “A Structure-Based Methodology for Analog Layout Generation,” Proc. of International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, July 2019 (SMACD-19)
        85. H.-Y. Chi, Z.-J. Lin, C.-H. Hung, C.-N. Liu and H.-M. Chen, “Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines,” Proc. of IEEE/ACM International Conference on Computer-Aided Design, November 2019 (ICCAD-19)
        86. C.-Y. He, K.-H. Tang, T.-S. Chen, K.-Y. Chang, C.-H. Lin, K. Sato, S.-J. Jou, P.-H. Chen, H.-M. Chen, B.-D. Rong, K. Itoh, “Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point5T Cell and Built-in Y Line,” Proc. of IEEE Asian Solid-State Circuits Conference, November 2019 (ASSCC-19)
        87. J.-R. Jiang, Y.-C. Kuo, Y.-H. Chen, and H.-M. Chen, “On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages,” Proc. of IEEE/ACM Design, Automation and Test in Europe, March 2020 (DATE-20)
        88. S.-H. Liou, S. Liu, R. Sun and H.-M Chen, “Timing Driven Partition for Multi-FPGA Systems with TDM Awareness,” Proc. of ACM International Symposium on Physical Design, March 2020 (ISPD-20) (Best Paper Award Nominee)
        89. H.-Y. Chang, H.-M. Chen, Y.-C. Kuo, H.-T. Tsai, Simon Y.-H. Chen, J.-R. Jiang, and Y.-Y. Chien, “Irregular Bumps Design Planning for Modern Ball Grid Array Packages,” Proc. of IEEE Electronic Components and Technology Conference, May 2020 (ECTC-20)
        90. M.-Y. Huang and H.-M. Chen et al., “A Design Flow for Micro Bump and Stripe Planning on Modern Chip-Package Co-Design,” Proc. of IEEE Electronic Components and Technology Conference, May 2020 (ECTC-20)
        91. A. Patyal, H.-M. Chen and P.-H. Lin, “Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization (LBR),” Proc. of ACM/IEEE Design Automation Conference, July 2020 (DAC-20)
        92. P.-T. Huang, T.-H. Tsai, P.-J. Yang, W. Hwang and H.-M. Chen, “Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs,” Proc. of IEEE International System on Chip Conference, September 2020 (SOCC-20)
        93. P.-H. Lin, H.-Y. Chi, A. Patyal, Z.-Y. Liu, J.-J. Zhao, C.-N. Liu and H.-M. Chen, “Achieving Analog Layout Integrity through Learning and Migration,” Proc. of IEEE/ACM International Conference on Computer-Aided Design, November 2020 (ICCAD-20) (Invited)
        94. H.-M. Chen et al., “On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications,” Proc. of IEEE/ACM International Conference on Computer-Aided Design, November 2020 (ICCAD-20) (Invited)
        95. Y.-Y. Huang, C.-T. Lin, W.-L. Liang and H.-M. Chen, ”Learning Based Placement Refinement to Reduce DRC Short Violations, ” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, April 2021 (VLSI-DAT-21)

 

    • Other non-EDA Papers
        1. L. F. Chien , H. T. Pu, M. C. Chen, H.-M. Chen and M. J. Lee, “Natural Language Information Retrieval with speech recognition techniques for network Chinese resources discovery,” Proceedings of the 1996 International Workshop on Information Retrieval with Oriental Languages (IROL 96)
        2. L. F. Chien , M. C. Chen, M. J. Lee , H.-M. Chen, T. Huang and H. T. Pu, “Speech and Natural Language Information Retrieval for Real-time Chinese Netnews Service,” Proceedings of the 1997 Int. Conf. On Computer Processing of Oriental Languages, Hong Kong, April 1997 (ICCPOL 97)